During the manufacturing of digital integrated circuits, a manufacturing defect may result in an unintentional resistive path between different signal nodes, between a signal node and a power supply node, or between a signal node and ground. One common test approach is to apply sequences of logical input signals and monitor the resulting output signals. As complexity grows, however, it becomes increasingly difficult to find an input signal sequence that correctly exercises all internal nodes of interest and that guarantees that an internal node fault will propagate to an output for detection. In addition, a node defect may not be detectable as a logical fault. For example, as a result of a resistive or shorted node, circuitry may simultaneously pull-up and pull-down the node. The result of the conflicting conductances may be an intermediate voltage that may or may not induce logic errors. Conflicting conductances may, however, result in a detectable increase in power supply current. For example, if a node is shorted to ground and a gate attached to the shorted node attempts to drive the shorted node to a supply voltage (or conversely, if a node is shorted to a supply voltage and a gate attempts to drive the shorted node to ground), the shorted node may cause a detectable increase in the current drawn by the integrated circuit. If the current change is detectable, the node fault may be detectable without having to propagate the fault to an output node. In addition, the node fault may be detectable even if no logical error is induced. Testing based on detecting an increase in power supply current is called quiescent current testing or IDDQ testing. For a collection of articles providing general background information, see Y. K. Malaiya and R. Rajsuman, Bridging Faults and IDDQ Testing, IEEE Computer Society Press, 1992.
In general, even though quiescent current testing may eliminate the need to propagate logical faults to output terminals, there is still a need to ensure that all nodes are driven both high and low during current testing. In general, multiple input signal sequences and many current tests are needed to test all nodes of interest. There is a need for a quiescent current test that ensures that all nodes of interest are driven both high and low during current testing without requiring propagation of sequences of input signals. There is a need for minimizing the number of current tests required.
As the term "quiescent" implies, quiescent current measurement must be performed at a time when transient currents have stabilized. Quiescent current testing is typically limited to static logic circuitry in which the system clock can be paused, in which there is negligible static current and in which at any given time every node is always actively driven to a supply voltage or to ground. Dynamic logic circuits typically store a logic level temporarily as a voltage on a charged node capacitance. The node capacitance charge must be periodically refreshed or the node capacitance may float to an intermediate voltage. Generally, for dynamic logic circuits, a current measurement requires a longer time than the refresh time for the dynamic logic. If the system clock is paused for dynamic logic circuits, internal nodes may float to intermediate levels that can cause multiple downstream transistors to turn on such that opposing transistors may attempt to simultaneously drive a node to a supply voltage and to ground. This may cause an increase in overall current which is not caused by a node fault. There is a need for a method of quiescent current testing in dynamic logic circuitry which is not affected by voltage drift during a paused clock period.
A general goal of integrated circuit testing is to complete the test as rapidly as possible to minimize manufacturing costs. Complex integrated circuits may require a significant amount of time to initialize the circuitry or to otherwise drive the circuitry to a known state. A quiescent current test may alter the logical state of the circuitry being tested which in turn may require a new initialization process after the quiescent current test is complete. Therefore, a quiescent current testing solution is desirable that preserves the dynamic logic states.